1. Field of the Invention
The present invention relates to memory devices and methods for storing information. More particularly, the invention relates to high density memory devices having non-volatile storage capability and methods for the high-density storage of information in non-volatile condition.
2. Description of the Prior Art
In the electrical art, devices for storing information can be generally classified as providing "volatile" or "non-volatile" storage of information. As known in the art and as used herein "volatile storage" is specifically defined to mean that the stored information will be lost in the absence of power supply voltages, whereas "non-volatile storage" is defined to mean that the information is retained in the absence of power supply voltages.
In the prior art, it was recognized that devices capable of non-volatile information storage offered considerable advantages in reliability because, in the event of a power failure, information stored therein would not be lost and use of the devices could be resumed without first regenerating the information. In earlier prior art, magnetic cores were typically employed as memory elements that stored binary information through control of magnetic flux changes in the core. However, the physical size and power requirements of such magnetic cores presented limitations and disadvantages as to their use.
Subsequently, electronic devices were developed that were capable of storing binary information in non-volatile condition. Of chief importance among these electronic devices are insulated-gate-field-effect-transistors (IGFET's) and, more particularly, metal-nitride-oxide-silicon (MNOS) transistors. MNOS transistors have been found to exhibit characteristic changes of threshold voltage in response to relatively high gate-to-source voltages (V.sub.GS), such that binary information can be stored in MNOS transistors by shifting the level of the threshold voltage. Specifically, it has been found that, when the oxide layer of a MNOS transistor is made very thin (as, for example, about 20 A), it is possible to selectively insert or remove electrical charge from traps in the nitride close to the nitride-oxide interface by applying a voltage across the gate insulator. The charge trapped in the insulator alters the threshold voltage of the transistor such that the threshold voltage is selectively shifted or switched by the application of the voltage across the gate insulator. The most positive threshold level places the transistor in a high conduction (HC) state, generally described by the symbol V.sub.HC, and the most negative threshold places the transistor in a low conduction (LC) state, generally described by the symbol V.sub.LC. When powers is removed from the transistor, the trapped charge remains in the composite insulator for long time periods such that the storage of information in accordance with the transistor threshold level is characterized as non-volatile. Storage of binary information in this manner is somewhat analogous to the storage of such information in magnetic cores but with the advantages that these devices require relatively little power, are extremely small, and easy to fabricate. Examples of such devices are shown and described in U.S. Pat. No. 3,683,335 to Cricchi et al., U.S. Pat. No. 3,889,287 to M. W. Powell; U.S. Pat. No. 3,845,327 to J. R. Cricchi; U.S. Pat. No. 3,836,894 to J. R. Cricchi; U.S. Pat. (Ser. No. 219,463) filed Jan. 20, 1972 to J. R. Cricchi; U.S. Pat. No. 3,908,182 to Lampe et al.; U.S. Pat. No. 3,877,055 to J. A. Fisher et al.; and U.S. Pat. No. 3,881,180 to W. M. Goshey, Jr.
A problem in the prior art has been that electronic devices that have been used as memory elements have been found to be subject to fatigue and tend to change their characteristics and parameters with use. For example, an MNOS memory transistor which does not incorporate any stress protection features can be expected to exhibit significant changes in pulse response and in threshold voltage decay rate after having been erased and written about 10.sup.6 times.
Accordingly, devices and methods have been developed whereby the life expectancy for non-volatile electronic memory devices would be improved. Some of these developments, such as U.S. Pat. No. 3,911,464 to Chang et al., were directed to modifications of the basic device. Other developments were directed to combining the non-volatile memory devices with other electronic devices which, although having only volatile storage capability, could perform many more storage operations.
As used herein, the term "memory cell" is defined to mean the circuitry required to store one binary bit of information, and the term "composite memory cell" is defined to mean a memory cell that includes a combination of non-volatile and volatile memory cells. Composite memory cells were intended to produce a memory cell that had both non-volatile storage capability and a long life expectancy. Examples of such composite cells are shown in U.S. Pat. No. 4,070,655 to F. L. Schurmeyer et. al.; U.S. Pat. No. 4,064,492 to F. L. Schuermeyer et al.; U.S. Pat. No. 3,831,155 to Tamaru et al.; and U.S. Pat. No. 3,916,390 to J. J. Chang et al. These composite cells provided memory storage for a single bit of binary information. During normal memory operation, the data was written and read from the volatile device of the composite cell. At some time during the use of the memory, such as on occurrence of a power failure, the information stored in the volatile cell was stored in the nonvolatile cell such that the information could be called back to the volatile cell at a later time.
A problem with the composite type of memory cell was that, with the requirement of more devices to comprise the cell, the memory cells became physically larger. Therefore, arrays of such composite memory cells provided a long-life memory having non-volatile storage capacity, but were relatively large in comparison to previous electronic non-volatile memories. Defining "information density" to be the number of information bits that can be stored in a unit area, the composite memory cells had relatively low information density in comparison to previous electronic non-volatile memories. Accordingly, there was a need in the prior art for an electronic memory that not only had non-volatile storage capability and a long life expectancy, but also had high information density.
A somewhat related problem in the prior art is the speed at which information can be stored into and retrieved from a memory cell. For example, the memory of a typical computer system is usually organized in a hierarchial fashion to achieve required capacity and performance at an acceptable cost. The memory includes a primary memory that is randomly word addressable, provides fast data access, and is relatively expensive; together with secondary and higher order memories that are generally addressable in a different fashion, and usually provide non-volatile storage. The higher memory levels have progressively larger capacity, slower access and lower cost. At each memory level, the hierarchy design of computer memories involves tradeoffs in terms of access time, capacity and cost.
In view of the hierarachial organization of computer memories, a known method of facilitating computer processing has been to partition the data and the computer program into fixed groups of words called a "page". Pages that contain data and program necessary for immediate processing are stored in the primary memory. When the computer cannot find a required item in the primary memory, a "page fault" occurs. In this event, a higher order memory is referenced to obtain the necessary page or pages, and the processing of the related program is terminated until the data or program is available in primary memory.
Computer idle time caused by delay in obtaining data from high order memory adversely affects the computer efficiency such that reduction of idle time is of major importance in both software and hardware design. Accordingly, an important development has been multiprogramming techniques in which a computer stores pages from several programs in the primary memory and jumps from program to program when input/output (I/O) is necessary, such that computing operations can be executed simultaneously with I/O operation. However, such multiprogramming techniques require considerable software expense in maintaining track of data and current operations.
The performance of a secondary and higher order memories is primarily characterized by the required time delay between reception of a request for stored information and the time when the information is available in primary memory. This time delay is comprised of access time and flow time. Access time is the delay between the reception of the request and the availability of the first data element of the information at the output of the memory. Flow time is the time required to transfer all the requested information from the memory output to the primary memory.
Accordingly, there also existed a need for memory devices and memory storage and retrival techniques having lower time delays for transferring data from high order memories to primary memory. Moreover, such devices and methods must afford the nonvolatile storage capability and also be economically competative with existing devices and methods.